Study of Etching Process of HARC(High Aspect Ratio Contact) Holes for 63nm DRAM Applications
碩士 === 國立暨南國際大學 === 光電科技碩士學位學程在職專班 === 100 === Semiconductor industry is a new technique industry. Recent years, it develops very soon in Taiwan, just as project of the Moore’s Law, the element size is continuing scaled down. Therefore, today the Integrated Circuit process technique becomes very...
Main Authors: | Chen, JuChun, 陳儒俊 |
---|---|
Other Authors: | 林佑昇 |
Format: | Others |
Language: | zh-TW |
Published: |
2012
|
Online Access: | http://ndltd.ncl.edu.tw/handle/79355448840293140637 |
Similar Items
-
An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process
by: Jaewon Park, et al.
Published: (2021-01-01) -
The Study of Yield Improvement in 30 nm DRAM Storage Node Contact PAD
by: Shih, Chao-Fu, et al.
Published: (2016) -
Failure Mode Analysis of Bit-Line Contact for 90 nm Deep Trench DRAM
by: Ta-Jung Su, et al.
Published: (2007) -
Embedded DRAM Deep Trench Etching Process for Yield Improvement
by: Jung-HungYeh, et al.
Published: (2013) -
The Study of Optimal Parameters for Contact Hole Etching Process by Design of Experiments
by: Yung-Tsang Chang, et al.
Published: (2006)