| Summary: | 碩士 === 國立暨南國際大學 === 光電科技碩士學位學程在職專班 === 100 === Semiconductor industry is a new technique industry. Recent years, it develops very soon in Taiwan, just as project of the Moore’s Law, the element size is continuing scaled down. Therefore, today the Integrated Circuit process technique becomes very complex. In order to increase the efficiency of computer, communication, and consumer electronics and pursue the lower cost of wafer, to reduce the size of complementary metal- oxide- semiconductor (CMOS) is a continued target for pursuing the technique improvement. Following along with the element size reduction, it would be expected to go into sub-nanometer processes with 45 nm and 32 nm, the thickness of gate dielectric which is made with SiO2 must be smaller than 1 um, and it could reach the requirement for element’s characteristic. In addition, the critical dimension (CD) of contact hole from the peripheral to cell must be smaller. However, due to the demand in the process, the thin film doesn’t decrease too much, and a depth of etch is still the same, but the critical dimension (CD) of the contact hole is reduced, so that the contact hole is easy to get some problems, such as un- open and punch which becomes a big challenge in the contact hole etch process.
This study is talking about etching process of HARC (High Aspect Ration Contact) holes for 63 nm dram applications. It adapts TEL etch equipment, reactive ion etching, by adjusting different etch parameters to form a HARC hole from peripheral to cell to get better etch profile to solve up-open and punch problems with critical dimension reduction. In addition, it lowers resistance unit of contact hole.
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