| Summary: | 碩士 === 國立暨南國際大學 === 電機工程學系 === 100 === The simulation and layout of the thesis is to achieve a 250MHz 10bits current steering DAC, and is expected to complete tape out by 0.18um 1p6m process provided by Taiwan Semiconductor Manufacturing Company provided . The circuit layout design has two parts - digital and analog. To reduce the glitch and differential nonlinearity (DNL), integral nonlinearity (INL) and to maintain the transfer curve monotonic the circuit is designed to be segmented structure, in which the highest 6bits MSB is the thermometer decoder and the lowest 4bits LSB is weighted binary code. The circuit is composed of 4 main parts: (1) digital circuit (2) clock drive, buffer (3) Deglitch Latch (4) current units. And current steering DAC output current do not need to output buffer can Directly drive the load resistance, so better than other architecture has speed advantages. Finally, first measurements to similar measurements of this structure TSMC 0.35μm the DAC chip for its measurement method and its results as a measurement of the paper as a reference.
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