A 10-bit 200-kS/s 0.7-µW Successive-Approximation Analog-to-Digital Converter
碩士 === 國立成功大學 === 電機工程學系專班 === 100 === This thesis presents the design of a 10-bit 200-kS/s successive-approximation analog-to-digital converter (ADC). A bypass window-technique is proposed to reduce the power consumption of the digital control circuits, comparator, and capacitor array significantly...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/42453527626104100781 |