| Summary: | 碩士 === 國立成功大學 === 電機工程學系碩博士班 === 100 === This thesis presents the proposed low-distortion sigma-delta modulator which is suitable for the applications in wireless communication system. In addition to high resolution, extending the bandwidth and decreasing the power consumption are also goals of this design. The loop filter processes quantization error only in conventional low distortion sigma-delta modulator. However, the quantizer and dynamic element matching circuit are hard to accomplish in non-overlapping time interval for high speed applications. In order to mitigate the timing issue, the feedback path timing is relaxed to half cycle of clock period in the proposed architecture. On the other hand, the power consumed by operational amplifiers dominates the power consumption of overall modulator. The integration phases of three integrators have been staggered. Thus, the integrators in three stages are realized by only one operational amplifier. The power consumption is reduced greatly. Besides, the data weighted averaging algorithm adopts in dynamic element matching circuit to eliminate the effect of mismatch among capacitors in DAC. Merged capacitor switching technique is introduced into implementation of the proposed dynamic element matching circuit. Hence, its complexity and area are reduced.
The proposed low-distortion third-order sigma-delta modulator is simulated in 90-nm 1P9M 1.2-V CMOS process technology. The circuit is operated under 80 MHz clock rate and 2.5 MHz signal bandwidth with a supply voltage of 1.2V. Simulation results show that a 79.62-dB SNDR and 12.93-bit resolution are achieved with 1.16-mW total power consumption under 16-X oversampling ratio. FOM is 29.66 fJ/conversion.
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