Design and Implementation of a Novel Multi-Level DC-AC Inverter

• Main Authors: Cheng-HanHsieh, 謝政翰
• Other Authors: Ming-Yang Cheng
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/70137228460447495746

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 100 === In this thesis, a novel multi-level DC-AC inverter is proposed. The proposed multi-level inverter generates seven levels AC output voltage with the appropriate gate signals design. Also, the low pass filter is used to reduce the total harmonic distortion of the sinusoidal output voltage. The switching losses and the voltage stress of power devices can be reduced in the proposed multi-level inverter. The operating principles of the proposed inverter and the voltage balancing method of input capacitors are discussed. Finally, a laboratory prototype multi-level inverter with 400 V input voltage and output 220 Vrms /2 kW is implemented. The multi-level inverter is controlled with sinusoidal pulse-width modulation (SPWM) by TMS320LF2407 digital signal processor (DSP). Experimental results show that the maximum efficiency is 96.9% and the full load efficiency is 94.6%.