A Statistic Approach to Synthesis High Variation-Tolerant Mesh for Constructing Low Power Clock Networks

• Main Authors: Yu-YunLee, 李玉雲
• Other Authors: Jai-Ming Lin
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/45859820660203496069

碩士 === 國立成功大學 === 電機工程學系碩博士班 === 100 === Due to its high tolerance to process-variation, clock mesh is a widely used structure in a clock network for high performance synchronous VLSI designs. Since mesh structure induces more capacitance, the mesh based clock network usually consumes more power than the tree based clock network. Therefore, we propose a Statistical approach to Synthesis a Mesh (SSM for short) for low power clock networks. In this thesis, a statistical approach is first proposed to determine a good mesh size based on sink capacitance distribution to achieve required clock skew constraint. Compared to the partition based approach [19] and [26], the statistical based method can achieve the same skew constraint using less wirelength in the resulting mesh. More importantly, it is efficient and general, which can be applied to an arbitrary design. In addition, this thesis also proposes a good clock network topology, which integrates a small balanced binary tree with a non-uniform clock mesh, to reduce capacitance in the bottom-level mesh as well as in the top-level clock tree. Compared to [19] and [26], which are two winning teams in the ISPD’10 Clock Network Synthesis Contest using the mesh structure, the clock networks generated by their approaches are about 1.51 and 2.36 larger than SSM on the benchmarks provided by the contest. Besides, SSM is very efficient, and it only requires 26.81 sec to construct a clock network in average.