Investigation of Electrical Characteristics in High Performance MOSFET Utilizing Mobility Enhancement Technology

• Main Authors: Po-ChinHuang, 黃博勤
• Other Authors: Shoou-Jinn Chang
• Format: Others
• Language: en_US
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/22616845797856017527

博士 === 國立成功大學 === 微電子工程研究所碩博士班 === 100 === Because of the continuous MOSFET scaling, carrier mobility becomes the key for maintaining Moore’s Law and booting CMOS performance. In order to obtain high performance MOSFET, mobility enhancement technologies are introduced and applied into state-of-the-art transistor structures. In this dissertation, we explore the electrical characteristics in high performance MOSFET using mobility technology, including biaxial and uniaxial strained-Si technologies, and hybrid orientation technology (HOT). First, we present the ion ionization efficiency (IIE) in biaxial strained-Si nMOSFETs and strained-SiGe pMOSFETs. As compared with bulk Si MOSFETs, the enhanced IIE in biaxial strained devices is attributed to the narrowing of band gap, i.e., a decrease in the threshold energy of II, taking account into the difference in source/drain junction depth in strained-Si nMOSFETs and increased mean free path of the hole in strained-SiGe pMOSFETs, respectively. Then, we explore the DC and low-frequency (1/f ) noise characteristics in uniaxial tensile strained-Si nMOSFETs with SMT process operated at room- and high-temperatures. It can observe that an approximately 7.2% drive current enhancement, lower gate leakage current, and improved 1/f noise characteristic in strained-Si nMOSFETs simultaneously. As temperature increased, strained-Si nMOSFETs exhibit less sensitivity of electrical characteristics to temperature. These are ascribed to the SMT process-induced tensile is truly transmitted into channel. The band splitting between the low-energy two out-of-plane (Δ2) valleys and high-energy in-plane (Δ4) valleys increase, leading to the reduced carrier scattering, and electron with the averaged lighter in-plane and heavier out-of-plane effective mass. Finally, we investigate the Si/SiO2 interface property of CMOS fabricated on hybrid orientation substrate with amorphization/templated recrystallization (ATR) method. Through physical and electrical analyses, it finds that ATR process-induced defects at the recrystallized (100) regions are further repaired by increasing defect-removal annealing time, resulting in the improvement of the Si/SiO2 interface of nMOSFETs. Besides, no effect on pMOSFETs fabricated on (110) regions are observed, meaning that modified ATR process can be adopted for fabricating the state-of-the-art CMOS on a HOT wafer.