Hardware Implementation of 1-D and 2-D One-Phase Sorted Rank Filter
碩士 === 國立成功大學 === 資訊工程學系碩博士班 === 100 === In image processing, we often handle the noisy image by using median or rank filter, or even a sequencer (sorted filter). Sequencer is not only capable of processing 2-dimensional image but also applicable to any algorithms which need sort. Moreover, hardware...
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ndltd-TW-100NCKU53920272015-10-13T21:33:37Z http://ndltd.ncl.edu.tw/handle/07585698693253634671 Hardware Implementation of 1-D and 2-D One-Phase Sorted Rank Filter 一維及二維之一階段排序器硬體設計 An-JiingChiang 姜安璟 碩士 國立成功大學 資訊工程學系碩博士班 100 In image processing, we often handle the noisy image by using median or rank filter, or even a sequencer (sorted filter). Sequencer is not only capable of processing 2-dimensional image but also applicable to any algorithms which need sort. Moreover, hardware implementation is able to increase the speed of the system. This paper proposes hardware architecture of 1-dimensional and 2-dimensional sorted rank filter. Their circuits process the input samples sequentially in word-level manner. At each clock cycle, they only need to put the input sample in the exact position for the purpose of maintaining the sorted result of the samples. This accomplishes the reuse concept. Unlike existing 1-dimensional or 2-dimensional filter implementations, our proposed methods consider the variable values of deletion and insertion to realize 1-dimensional and 2-dimensional architecture. In addition, 1-dimensional architecture can be extended to various sizes by using a software IP generator. We utilize Verilog and Altera Quartus to implement and verify our 1-dimensional and 2-dimensional circuits respectively. Both the 1-dimensional and 2-dimensional architectures have linear complexity, minimal latency, and one-phase processing procedure. The experiments also show high frequency and high throughputs of our designs. Pei-Yin Chen 陳培殷 2012 學位論文 ; thesis 42 en_US |
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碩士 === 國立成功大學 === 資訊工程學系碩博士班 === 100 === In image processing, we often handle the noisy image by using median or rank filter, or even a sequencer (sorted filter). Sequencer is not only capable of processing 2-dimensional image but also applicable to any algorithms which need sort. Moreover, hardware implementation is able to increase the speed of the system.
This paper proposes hardware architecture of 1-dimensional and 2-dimensional sorted rank filter. Their circuits process the input samples sequentially in word-level manner. At each clock cycle, they only need to put the input sample in the exact position for the purpose of maintaining the sorted result of the samples. This accomplishes the reuse concept. Unlike existing 1-dimensional or 2-dimensional filter implementations, our proposed methods consider the variable values of deletion and insertion to realize 1-dimensional and 2-dimensional architecture. In addition, 1-dimensional architecture can be extended to various sizes by using a software IP generator.
We utilize Verilog and Altera Quartus to implement and verify our 1-dimensional and 2-dimensional circuits respectively. Both the 1-dimensional and 2-dimensional architectures have linear complexity, minimal latency, and one-phase processing procedure. The experiments also show high frequency and high throughputs of our designs.
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author2 |
Pei-Yin Chen |
author_facet |
Pei-Yin Chen An-JiingChiang 姜安璟 |
author |
An-JiingChiang 姜安璟 |
spellingShingle |
An-JiingChiang 姜安璟 Hardware Implementation of 1-D and 2-D One-Phase Sorted Rank Filter |
author_sort |
An-JiingChiang |
title |
Hardware Implementation of 1-D and 2-D One-Phase Sorted Rank Filter |
title_short |
Hardware Implementation of 1-D and 2-D One-Phase Sorted Rank Filter |
title_full |
Hardware Implementation of 1-D and 2-D One-Phase Sorted Rank Filter |
title_fullStr |
Hardware Implementation of 1-D and 2-D One-Phase Sorted Rank Filter |
title_full_unstemmed |
Hardware Implementation of 1-D and 2-D One-Phase Sorted Rank Filter |
title_sort |
hardware implementation of 1-d and 2-d one-phase sorted rank filter |
publishDate |
2012 |
url |
http://ndltd.ncl.edu.tw/handle/07585698693253634671 |
work_keys_str_mv |
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