| Summary: | 碩士 === 國立成功大學 === 資訊工程學系碩博士班 === 100 === In image processing, we often handle the noisy image by using median or rank filter, or even a sequencer (sorted filter). Sequencer is not only capable of processing 2-dimensional image but also applicable to any algorithms which need sort. Moreover, hardware implementation is able to increase the speed of the system.
This paper proposes hardware architecture of 1-dimensional and 2-dimensional sorted rank filter. Their circuits process the input samples sequentially in word-level manner. At each clock cycle, they only need to put the input sample in the exact position for the purpose of maintaining the sorted result of the samples. This accomplishes the reuse concept. Unlike existing 1-dimensional or 2-dimensional filter implementations, our proposed methods consider the variable values of deletion and insertion to realize 1-dimensional and 2-dimensional architecture. In addition, 1-dimensional architecture can be extended to various sizes by using a software IP generator.
We utilize Verilog and Altera Quartus to implement and verify our 1-dimensional and 2-dimensional circuits respectively. Both the 1-dimensional and 2-dimensional architectures have linear complexity, minimal latency, and one-phase processing procedure. The experiments also show high frequency and high throughputs of our designs.
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