Mercurius: A High Speed and Flexible AMBA Architecture

• Main Authors: Chia-YangLin, 林家洋
• Other Authors: Wen-Long Chin
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/55918301863390426158

碩士 === 國立成功大學 === 工程科學系碩博士班 === 100 === With the advance in silicon technology, more and more complicated hardware components can be integrated into a single chip, so the System-on-Chip (SoC) design method becomes popular in recent years. Advanced Micro-controller Bus Architecture(AMBA) is an on chip bus architecture widely used in SoC. It provides a standard bus protocol to connect every component on the chip. However, AMBA cannot support multiple outstanding transactions and all the components share the same bus channel. If a slave is not ready to respond, that means no other transaction can bypass the blocked one, which leads to a huge reduction of the performance. To address this issue, this paper proposes a shared-memory switching architecture based on AMBA bus protocol, which is named Mercurius. It can seamless replace the traditional bus architecture, that is Mercurius is compatible of the existed device without any modification. All the transactions initiated by masters are stored in the shared-memory, and then the transactions will be dispatched to the slaves after dynamically inquiring the routing table. The system can achieve the optimal performance and support multiple outstanding transactions owing to the statistical multiplexing property of shared-memory, therefore all the master and slave pairs ideally are able to transfer data parallel, which can bypass the blocked one. Under successive and slow transactions, the flow control mechanism not only prevents the shared-buffer overflow but also allocates the resources evenly among all devices. The shared-memory architecture can absorb all the transactions initiated by masters and send them out to the slaves at the same time like a virtual point-to-point characteristic, hence the data transfer bandwidth of Mercurius is several times than traditional bus-based interconnect. Also it can allows a master-to-master type of communication between hardware components which can reduce the extra connection area. The performance is evaluated by the register-transfer level models which are implemented with TSMC 90nm silicon technology. The design specification is 8x8(that is the system support eight devices, which can be reconfigured by user). The simulation results show that the data transfer bandwidth is at least three times than AMBA Advanced High-performance(AHB) even in the best condition(the slave response time are zero delay). If a slave is not ready to respond, that means no other transaction can bypass the blocked one, then simulation results shows that the data transfer bandwidth is at least four times than AMBA AHB.