Analysis of residual stress and warpage induced by soldering in monocrystalline silicon wafers

• Main Authors: Chi-HungSu, 蘇季鴻
• Other Authors: Chi-Ming Lai
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/72262252924623463400

碩士 === 國立成功大學 === 土木工程學系碩博士班 === 100 === In recent years, PV manufacturing develops rapidly, and as the result, it gradually leads to the decreasing of semiconductor material. Solar cell as semiconductor material undergoes vast reduction in cell thicknesses, yet greater dimension as the consequence of costs considerations is inevitable. Solar cell also requires the electric conductivity and power output, which can be achieved through the soldering process. However, the process usually lead to substantial increase of warpage in silicon wafer, which is not good for the packing process of wafer itself and may seriously damage and reduce wafer life use. Therefore, how to reduce warpage and residual stress in wafer soldering process will be an important issue in the future. In this paper, both finite element simulation from ANSYS and experimental measurement were conducted to analyze the behavior of the soldering process in monocrystalline silicon wafers warpage. Comparison between both methods was carried out to verify the accuracy of numerical simulation analysis process. The results of verified numerical simulation method were utilized to assess different geometric parameters of monocrystalline silicon wafers, which affect it structural behavior in the soldering process. Furthermore, investigation of the crack variations of silicon wafers under the specified different geometry parameters regarding the stress behavior and intensity factor was also examined in this research. Eventually, in accordance with the results from experiment and numerical simulation, conclusions and recommendations can be made as future references concerning silicon wafer soldering process.