| Summary: | 碩士 === 國立中興大學 === 電機工程學系所 === 100 === In this thesis, a hardware sharing architecture to perform the multi-standard deblocking filter that support VP8 and H.264/AVC is proposed. First, a reorganization of deblocking filter is used to derive a common architecture which is suitable for H.264/AVC and VP8. The proposed design is then reused for the whole filtering. To further reduce the computational complexity, highly sharing architecture is also presented. In order to save the size of the on-chip memory, a memory sharing architecture of the deblocking filter and motion compensation is introduced. We also reorganize the processing order of filtering to reduce the total on-chip memory size.
According to the experimental results, the adopted hardware sharing architecture saves 63.3% of shifters, 77.4% of adders and 100% of multipliers totally. The overall PSNR drops less than 1% on the VP8 decoder for low complexity applications. Finally, a hardware implementation using TSMC 0.18 μm cell library is performed. The clock frequency of the proposed hardware is working at 130 MHz to perform deblocking filter for supporting Full HD 1080P@30fps. The implementation results show that the gate count of this architecture adopted on VP8 and H.264/AVC video codec system is 43.2K.
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