| Summary: | 碩士 === 國立中興大學 === 電機工程學系所 === 100 === Due to the prosperous development of VLSI and wireless communication technology, the solution of Multiple-Input Multiple-Output (MIMO) Orthogonal Frequency Division Multiplexing (OFDM) systems has become one of key technologies of wireless communications in recent years. The closed-loop MIMO-OFDM architecture is enhanced by employing precoding techniques, the channel state information at transmitter (CSIT) can be obtained via feedback from the receiver. Therefore, the scheme not only effectively improves performance of bit error rate (BER), but also can greatly reduce the complexity of the signal detector. The precoding techniques can be accomplished by applying matrix factorization methods such as singular value decomposition (SVD), geometric mean decomposition (GMD), and uniform channel decomposition (UCD).
In this thesis, we present unified work, which combines QRD for signal detection and GMD for precoding techniques, into a unified design. It supports a MIMO system with the number of antennas upto 4 × 4. Two remarkable merits of this chip are that, first, it supports matrix factorizations with a constant throughput, and second, it reduces the computational complexity at both the algorithm level and the hardware level. In the algorithm aspect, we proposed a novel GMD computing scheme based on a divide-and-conquer approach. It not only avoids the operational convergence issues of the conventional SVD, but also alleviates the permutation operations required by the traditional GMD schemes. In addition, it can simultaneously achieve computational complexity reduction and computing parallelism improvement. According to the results of algorithm mapping, we evaluate various parallel, pipelined architectures to derive our hardware design. We further employ the low complexity coordinate rotations digital computers (CORDICs) design to simplify the arithmetic units. Moreover, various chip designs and implementation skills are introduced to boost the operating frequency and to lower the computational complexity. Implementation results for a 4 × 4 QRD / GMD chip in TSMC 90-nanometer CMOS process indicate that this chip design has a chip area of 3.29 mm2 and can compute a 4 × 4 QRD or 4 × 4 GMD every 4 cycles at a clock frequency of 125 MHz. The total power consumptions are 87.5 mW and 148.4 mW respectively in each mode. This design can provide a throughput of 31.25M matrix decompositions per second.
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