| Summary: | 碩士 === 崑山科技大學 === 電子工程研究所 === 100 === In this thesis, the VHF and UHF bands oscillator which mainly composed of four cascaded differential double delay ring oscillator. The VCO (Voltage-Controlled Oscillator) is also applied on PLL. The VCO with high tuning range, and low phase noise, Their output frequency will be 3372 MHz, 2272 MHz under 0.9 volts and 1.8 volts respectively. We integrate voltage controlled oscillator and phase frequency detector, charge pump, low-pass filter, and frequency divider to implement a PLL (Phase-Locked Loop) circuit. The VCO circuits are simulated and verified by H-Spice, with tsmc 0.18μm technology. For PLL circuit is simulated by H-Spice only.
In the simulated PLL circuit, voltage controlled oscillator has high tuning range, control voltage with 0.9V to 1.8V. The tuning frequency is from 2272MHz to 3372MHz. The PLL locked frequency is 50MHz. We had implemented PLL IC layout and executed post layout simulation. For Low-Pass Filter included in PLL, the capacitor is created in PMOS and NMOS type respectively. The complete PLL including it’s on-chip loop filter occupies 371.35x362.95μm2 chip area.
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