Testable Design For AC-Coupling Interconnection In High-Speed Serial Links Applications
碩士 === 義守大學 === 電子工程學系 === 100 === More and more functionality has been integrated into single chips leading eventually to system-on-chip (SoC) implementations. However, a SoC may not always be the optimum solution due to extensive die size, number of interconnects and problems with technology compa...
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| Format: | Others |
| Language: | zh-TW |
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2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/42540546405408568506 |
| Summary: | 碩士 === 義守大學 === 電子工程學系 === 100 === More and more functionality has been integrated into single chips leading eventually to system-on-chip (SoC) implementations. However, a SoC may not always be the optimum solution due to extensive die size, number of interconnects and problems with technology compatibility and migration. Three-dimensional (3D) system integration is one of the key approaches to realize “More than Moore” that can provide continuous growth without relying on simple device scaling. 3D vertical integration of chips can be achieved in a variety of different ways including Through Silicon Via (TSV) or alternating current (AC) capacitive coupling in contactless communication. The use of AC capacitive coupling does reduce the mechanical stress as compared with using TSV technology. This thesis describes a chip-to-chip circuit design suitable for three-dimensional integrated circuit (3D IC) stacked applications. The proposed AC-coupled circuit of chip-to-chip communication was simulated using SPICE with TSMC 0.18 um CMOS 1P6M technology file. The simulation results indicated the proposed differential signal circuit is not only with the self-test characteristics but also suitable for 3DIC stacked applications with differential input signals up to 1.1 Gbps.
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