Design and Implementation of DLL-Based Pulse-Width Controlled Loop
碩士 === 華梵大學 === 電子工程學系碩士班 === 100 === Abstract Delay-locked loop (DLL) has been widely used in clock circuit. The DLLs advantage is the unconditional stability and fast locking process compared with Phase-lock loop (PLL), but have some problems such as the locked range is limited, harmonic lock...
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/82201287325264115352 |