Design And Implementation Of High-Bandwidth Phase-Locked Loop
碩士 === 華梵大學 === 電子工程學系碩士班 === 100 === As time advances, electronic products have emerged in recent years, some electronic products require a higher clock, but the nature clock generator - quartz can not provide higher frequency, so the value of phase-locked loop revealed, we can produce a higher fre...
Main Authors: | Jian-Ji Zhang, 張見吉 |
---|---|
Other Authors: | Chi-Nan Chuang |
Format: | Others |
Language: | zh-TW |
Published: |
2012
|
Online Access: | http://ndltd.ncl.edu.tw/handle/01821401841053171489 |
Similar Items
-
Design and Implementation of Phase-Locked Loop With Cyclic Clock Generator to Enhance Loop-Bandwidth
by: Chuang,Yi Hsien, et al.
Published: (2012) -
Design and Implementaion of CMOS Adaptive-Bandwidth Phase-Locked Loops
by: chih-chiang liao, et al.
Published: (2005) -
Design of Phase-Locked Loop With Reference Clock Injection to Improve Loop-Bandwidth
by: Kao, Chen-hsiang, et al.
Published: (2016) -
Adaptive Bandwidth All-Digital Phase-Locked Loop chip design
by: Yi-Herng Lee, et al.
Published: (2009) -
The Design of High Speed Digital Frequency Synthesizer and All-Digital Phase-Locked Loop with an Adaptive Bandwidth
by: Chen-Feng Chen, et al.
Published: (2011)