A Power-Aware NoC Design Using Central Look-ahead Dynamic Buffers Management
碩士 === 逢甲大學 === 資訊工程所 === 100 === As the technology of production process makes significant progress, the number of units contained in the single chip substantially raises. Therefore, multi-core system, the kind of system architecture which contains several cores in one single chip, becomes more and...
Main Authors: | Bo-Yi Shiu, 許博益 |
---|---|
Other Authors: | none |
Format: | Others |
Language: | zh-TW |
Published: |
2012
|
Online Access: | http://ndltd.ncl.edu.tw/handle/19521519565586070795 |
Similar Items
-
Low Power NoC Router Design Using Buffer Merging Algorithm
by: Hao-Tse Chen, et al.
Published: (2012) -
STT-MRAM Based NoC Buffer Design
by: Vikram Kulkarni, Nikhil
Published: (2012) -
The network calculator for NoC buffer space evaluation
by: Nadezhda Matveeva, et al.
Published: (2015-04-01) -
Buffer insertion in large circuits using look-ahead and back-off techniques
by: Waghmode, Mandar
Published: (2007) -
QoS-Aware Packet Scheduling by Looking Ahead Approach
by: Wen,Yung-Chuan, et al.
Published: (2008)