A Power-Aware NoC Design Using Central Look-ahead Dynamic Buffers Management

• Main Authors: Bo-Yi Shiu, 許博益
• Other Authors: none
• Format: Others
• Language: zh-TW
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/19521519565586070795

碩士 === 逢甲大學 === 資訊工程所 === 100 === As the technology of production process makes significant progress, the number of units contained in the single chip substantially raises. Therefore, multi-core system, the kind of system architecture which contains several cores in one single chip, becomes more and more popular. The demand for multi-core system''s communicating capability will definitely increase. Producing mass flow between cores easily results in problems of transmission delay due to the traffic contentions. Moreover, as the variation of applications extends, the functions that the SoC should support also increased. Network-on-Chip (NoC) can solve this communicational problem in multi-core SoCs. In the traditional router, each input port will be assigned a fixed number of virtual channels. When the traffic flow in each input port is unbalanced, the performance of the router is limited by the congested input port. In this way, the performance of the NoC will decrease. Therefore, we hope to solve this problem by the centralized management of virtual channels with look-ahead packet transmission policy to enhance the performance of the entire NoC. In addition, the buffers in the router consume a large amount of dynamic power. In the thesis, we also present a look-ahead policy to control virtual channel and buffer for dynamic power management.