| Summary: | 碩士 === 中原大學 === 電子工程研究所 === 100 === Minimizing TSV (Through-Silicon-Via) number is very important in 3D IC design, because TSV will increase the cost and the area, impact the circuit reliability, and reduce the die yield. There is a demand to reduce TSV number effectively in 3D IC design. In this thesis, we introduce the die stacking selection for TSV number minimization in high-level synthesis stage. There are three types of die stacking: face-to-face, face-to-back, back-to-back. We prefer the face-to-face stacking for the adjacent layers which have the most interconnects in order to minimize TSV number. We propose an integer linear programming (ILP) approach to solve this problem optimally. Experimental results consistently show that our approach can effectively reduce the TSV number in 3D IC Design.
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