| Summary: | 碩士 === 長庚大學 === 電機工程學系 === 100 === This thesis intends to discuss on how to construct an analog-to-digital conveter (ADC) by using the conversion of time-domain signals. We try to transform the analog voltage signal into digital time-pulse signal hence to form the digitally assisted analog circuit design. In theorical view, while the characteristic length of CMOS gates continuously shrinks to the nano-meter scale, the variations of analog signal increase, the current leakage of gates increases, and the open loop gain decreases…etc., more and more disadvantages occur. Since the accuracy and stability of analog voltage have been decreased ever, researchers want to use the digital signals and circuits to assist traditional analog structures with their advantage of scaling, for example, faster gates and lower power.
Here we construct a conversion system including multiphase voltage-controlled oscillator (VCO), 6-bit time domain analog-to-digital converter (coarse controller), and 6-bit multiphase time-to-digital converter (fine controller). The VCO oscillates at 1 GHz with 16 phases for the fine controller and a frequency divider that provides the counting frequency and sampling frequency for the system. The coarse controller transforms the analog voltage input into time-pulse signals by the ramp generator. The combination of coarse controller and ramp calibrator has enhanced the reliablility of the ramp hence makes the conversions under accurate range of voltage. The fine controller uses the 16 phases from VCO and combines the novel phase expander circuit, it not only increases the resolution, but also has the advantages such as monotonicity of phase triggering and variations resisting due to the synchronization of phases and sampling frequency. The fine controller collects the time residue of the coarse conversion and calculates the time residue to gain extra resolution thus increase the overall accuracy of the system.
This thesis uses the TSMC 0.18μm 1P6M Mixed Signal process to tapeout, the supply voltage is 1.8 V, the sampling frequency is 1 MHz, the counting frequency is 256 MHz, and the phase frequency is 1.024 GHz. The total power dissipation measured is 50.7 mW, the chip size (including pads) is 1.02 mm2, the core circuit size is 0.25 mm2. By simulation: The input signal is about 10 KHz and the results of coarse controller are 36.3 dB for signal-to-noise-and-distortion ratio (SNDR) and 41.5 dB for spurious-free dynamic range (SFDR). The fine controller has differential nonlinearity (DNL) less than 0.25 LSB and integral nonlinearity (INL) less than 0.48 LSB. By measurement: The jitter of the VCO is 10 ps under 10,000 hits of clock, and the dynamic verification has obtained 36.3 dB for SNDR, 44.8 dB for SFDR, and 5.74 bits for ENOB.
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