The Implementation of Lane Detection Recognition By SOPC Platform

• Main Authors: Yu Zen Chen, 陳煜仁
• Other Authors: M. J. Jeng
• Format: Others
• Published: 2012
• Online Access: http://ndltd.ncl.edu.tw/handle/64465550625586515378

碩士 === 長庚大學 === 電子工程學系 === 100 === In this paper, we use a SOPC Platform, which includes 5 mega pixel CMOS camera package and 4.3 inch LCD touch panel module, to verify the performance of lane detecting recognition. The SOPC design and implementation are carried out by a SOPC builder, which is generated by Quartus II Software includes a NIOS II Processor, an image transmission channel, a SDRAM Controller, a JTAG UART module and a few parallel I/O interfaces. To construct the real-time image transmission channel, we design two Avalon-MM master ports on input and output interfaces to connect with the slave port of SDRAM Controller. This design hardware channel can initiate data transferring by itself. Further, NIOS II Processor can access SDRAM randomly and do the lane detecting algorithm processing simultaneously. The lane detecting recognition system is implemented by hardware and software co-design successfully. The experimental results exhibit the processing speed of only 6~7 frames per second. It can be attributed to the speed limitation of SOPC platform, Altera DE2-70, which the maximum system clock is restricted to 150 MHz. One can use more advanced hardware platform (For example, the system clock of 500MHz) and high speed DDRRAM. The processing speed of 20 frames per second will be achieved by this proposed design.