Automatic Ratioed Capacitor Layout Generation Considering Device Matching and Parasitic Minimization
碩士 === 國立中正大學 === 電機工程研究所 === 100 === In analog layout design, the accuracy of capacitance ratios correlates closely with both the matching properties among the ratioed capacitors and the induced parasitics due to interconnecting wires. However, most of the previous works only emphasized the matchin...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2012
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| Online Access: | http://ndltd.ncl.edu.tw/handle/12768027241351901597 |