| Summary: | 碩士 === 國立中正大學 === 電機工程研究所 === 100 === In analog layout design, the accuracy of capacitance ratios correlates closely with both
the matching properties among the ratioed capacitors and the induced parasitics due to
interconnecting wires. However, most of the previous works only emphasized the matching
properties of a common-centroid placement but ignored the induced parasitics after
it is routed. This thesis addresses the parasitic issue in addition to device matching during
common-centroid capacitor layout generation. To effectively minimize the routinginduced
parasitics, a novel common-centroid placement style, distributed connected unit
capacitors, is presented. Based on the placement style, the ratioed capacitor layout generation
flow and algorithms are proposed to simultaneously optimize the matching properties
of a common-centroid placement and minimize the induced parasitics. Experimental
results show that the proposed approach can greatly reduce area, wirelength, and routinginduced
parasitics, and guarantee the best matching quality after routing.
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