| Summary: | 碩士 === 國立中正大學 === 資訊工程研究所 === 100 === Nowadays, people require high quality video/image service in a more eager way. One movie or one ball game could not be filmed by only one camera. Multi cameras would be used simultaneously to get different view angles. As a result, there are much more video data needed to compress. If we adopt the past video coding standards, we need to process a laige amount of video data. The ITU-T formulates the Multi-view Video Coding (MVC) Standard which takes advantage of video data dependency from different views to reduce the quantity of data to be processed. The proposed thesis named “A View-Scalable Multi-view Decoder Architecture Design” is able to decode the video which contents different views of multi-view video and supports the view-scalable flexibility. With this feature, SoC designers could not only adjust the number of MVC decoder cores and set the firmware parameters according to system requirements. This feature also benefits to adopting 3D IC packaging or implementation by exploiting high bandwidth SDRAM access.
In thsis proposed system, we are able to achieve two-view HD video decoding in real-time, so, we are able to use four decoder cores together for eight-view MVC video decoding. According to proposed design, we can achieve the demands of view-scalable multi-view decoder systems and make use of both the flexible stacking and high bandwidth access in 3D IC implementation. The proposed work is one feasible solution to approach flexible multi-view video decoder systems.
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