Synthesizing SystemC Programs into Synchronous Circuits
碩士 === 大同大學 === 資訊工程學系(所) === 99 === The design complexity to build SOC (System On a Chip) products is increasing and becoming more complex with the advance in technology. One promising way to solve the design complexity or productivity gap is high-level synthesis. SystemC is the IEEE standard to su...
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| Format: | Others |
| Language: | zh-TW |
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2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/98832976950472479672 |
| Summary: | 碩士 === 大同大學 === 資訊工程學系(所) === 99 === The design complexity to build SOC (System On a Chip) products is increasing and becoming more complex with the advance in technology. One promising way to solve the design complexity or productivity gap is high-level synthesis.
SystemC is the IEEE standard to support high-level synthesis. This thesis proposes an efficient method to translate SystemC programs into synchronous sequential circuits based on a graph notation. In particular, the SystemC programs are translate into a set of sub-graphs. Each sub-graph corresponds to a state in finite state machine. The sub-graphs are then translated into VHDL codes which are verified in Altera Quartus tool.
The experimental results show that the circuits synthesized by our translation methodology have the low worst case delay and have larger number of states.
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