Design and Implementation of Decimal Floating Point Hardware Accelerators on Nios II Platform

• Main Authors: Heng-Wei Chang, 張恆偉
• Other Authors: Fu-Chiung Cheng
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/64110809443923029047

碩士 === 大同大學 === 資訊工程學系(所) === 99 === Floating Point Units are a vital part of digital systems. Recently, there is increasing interest in decimal floating-point arithmetic research due to many commercial and financial-based applications which require Decimal Floating Point arithmetic. The problem of using binary floating-point arithmetic in commercial and financial calculations is that most decimal floating-point numbers cannot be represented exactly in binary floating-point formats, and thus unacceptable errors may occur in the course of the computations. Therefore, these applications usually use software library instead, such as Java’s BigDecimal and C#’s Decimal, suffering from performance penalty. Hardware decimal arithmetic units now are becoming an integral part of recently commercialized general purpose processors. This thesis designs and implements both software algorithms and hardware acceleration of Decimal Floating Point Arithmetic for Nios II platform. The experimental results show that C2H hardware accelerator, Custom Peripheral and Custom Instruction are 37 to 47, 96 to 447 and 976 to 4542 times faster than software functions, respectively.