| Summary: | 博士 === 國立臺北科技大學 === 電腦與通訊研究所 === 99 === Electronic products increasingly require high speed, high density, and low-voltage operation. The power-delivery system could be affected by input noise to the point that it becomes unstable. Simultaneous switching noise (SSN) is a major factor that interferes with power integrity. SSN has become a serious issue that must be addressed to ensure system stability during the short rise- and fall-times of the logic transient states. Most traditional designs have generally used decoupling capacitors to reduce SSN. Although decoupling capacitors cannot effectively alleviate the problem of SSN, they have been used in the HP Simulation Program with Integrated Circuit Emphasis (HSPICE) model for reducing SSN. These capacitors become equivalent series inductances when the system operates at high frequencies. It works against reducing SSN. Therefore, the enhanced I/O buffer information specification (IBIS) model which is able to effectively alleviate the problem of SSN using an evaluation based on the enhanced IBIS model with decoupling capacitors and a high-frequency low-impendence circuit is required to employ. The experiments show that the new method can reduce noise more than 73.2%, 58.3%, 25.7%, and 59.8% comparing with other methodologies including IBIS, traditional decoupling capacitors, IBIS with a high-frequency low-impendence circuit, and HSPICE, respectively.
The differential I/O buffer information specification (D-IBIS) model uses equivalent circuits to describe the behavior of an integrated circuit. A novel method for effectively reducing SSN evaluated by an enhanced D-IBIS model with decoupling capacitors and a high-frequency low-impendence circuit is applied. The experiments show that the new method can reduce noise by about 40－64% comparing with traditional design methodologies.
This thesis presents a straightforward approach for synthesizing a structural VHDL description of an asynchronous circuit from a behavioural VHDL description. The asynchronous circuit style is based on micropipelines, a style used to develop asynchronous microprocessors. The work presented in this thesis demonstrates that VHDL can be used to describe the behaviour of micropipelined systems. It also shows a comparison of 2-phase and 4-phase implementations in transistor count, speed, and energy. At the high level the computations of a whole system can be treated as one computation block with micropipelined latches. This simple structure helps the designer to estimate the expected behaviour of an abstract system as early as possible using a VHDL simulator.
The synthesizer can produce 2-phase and 4-phase structural VHDL and Verilog micropipelines. A comparison of 4-phase and 2-phase micropipelines using VHDL is also presented. From the simulations of the various configurations some insight is obtained. By carefully partitioning the computations into several stages of a 2-phase micropipeline, the circuit will speed up. Carefully partitioning the computations into several stages of a 4-phase micropipeline will not give as much speed-up.
The synthesized circuits are taken through to schematics and layouts in the Cadence design environment. Some test examples are presented to show how the synthesizer works. Postlayout simulation using TimeMill is also presented in this thesis. In summary, a design environment for asynchronous circuits has been established based upon the micropipeline style and VHDL, a standard hardware description language.
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