Study and Design of a Variable Frequency Synchronous Rectified VRM with Phase Reduction Optimization

碩士 === 國立臺北科技大學 === 電機工程系研究所 === 99 === This thesis proposes a novel control method that combines automatic phase reduction with switching frequency modulation and applies to the synchronous rectified buck converter on motherboards. The proposed novel control method decreases phases and increases sw...

Full description

Bibliographic Details
Main Authors: Jui-Chien Wang, 王瑞乾
Other Authors: 歐勝源
Format: Others
Language:zh-TW
Published: 2011
Online Access:http://ndltd.ncl.edu.tw/handle/w456v9
id ndltd-TW-099TIT05442018
record_format oai_dc
spelling ndltd-TW-099TIT054420182019-05-15T20:42:27Z http://ndltd.ncl.edu.tw/handle/w456v9 Study and Design of a Variable Frequency Synchronous Rectified VRM with Phase Reduction Optimization 具有降相最佳化之變頻同步整流 VRM 研製 Jui-Chien Wang 王瑞乾 碩士 國立臺北科技大學 電機工程系研究所 99 This thesis proposes a novel control method that combines automatic phase reduction with switching frequency modulation and applies to the synchronous rectified buck converter on motherboards. The proposed novel control method decreases phases and increases switching frequency in light loads, on the contrary, increases phases and decreases switching frequency in heavy load. Due to the proposed novel control method, it can further improve output voltage ripple with phase reduction and increase the efficiency in light loads. To match the required output voltage specifications, a load current threshold is predetermined and the switching frequency is fixed as the load current is higher than the threshold. Finally, this paper implements an eight-phase synchronous rectified buck converter, compared to conventional constant frequency techniques, the efficiency can be increased up to 30% for eight-phase one under the proposed novel control method. 歐勝源 2011 學位論文 ; thesis 65 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 國立臺北科技大學 === 電機工程系研究所 === 99 === This thesis proposes a novel control method that combines automatic phase reduction with switching frequency modulation and applies to the synchronous rectified buck converter on motherboards. The proposed novel control method decreases phases and increases switching frequency in light loads, on the contrary, increases phases and decreases switching frequency in heavy load. Due to the proposed novel control method, it can further improve output voltage ripple with phase reduction and increase the efficiency in light loads. To match the required output voltage specifications, a load current threshold is predetermined and the switching frequency is fixed as the load current is higher than the threshold. Finally, this paper implements an eight-phase synchronous rectified buck converter, compared to conventional constant frequency techniques, the efficiency can be increased up to 30% for eight-phase one under the proposed novel control method.
author2 歐勝源
author_facet 歐勝源
Jui-Chien Wang
王瑞乾
author Jui-Chien Wang
王瑞乾
spellingShingle Jui-Chien Wang
王瑞乾
Study and Design of a Variable Frequency Synchronous Rectified VRM with Phase Reduction Optimization
author_sort Jui-Chien Wang
title Study and Design of a Variable Frequency Synchronous Rectified VRM with Phase Reduction Optimization
title_short Study and Design of a Variable Frequency Synchronous Rectified VRM with Phase Reduction Optimization
title_full Study and Design of a Variable Frequency Synchronous Rectified VRM with Phase Reduction Optimization
title_fullStr Study and Design of a Variable Frequency Synchronous Rectified VRM with Phase Reduction Optimization
title_full_unstemmed Study and Design of a Variable Frequency Synchronous Rectified VRM with Phase Reduction Optimization
title_sort study and design of a variable frequency synchronous rectified vrm with phase reduction optimization
publishDate 2011
url http://ndltd.ncl.edu.tw/handle/w456v9
work_keys_str_mv AT juichienwang studyanddesignofavariablefrequencysynchronousrectifiedvrmwithphasereductionoptimization
AT wángruìgān studyanddesignofavariablefrequencysynchronousrectifiedvrmwithphasereductionoptimization
AT juichienwang jùyǒujiàngxiāngzuìjiāhuàzhībiànpíntóngbùzhěngliúvrmyánzhì
AT wángruìgān jùyǒujiàngxiāngzuìjiāhuàzhībiànpíntóngbùzhěngliúvrmyánzhì
_version_ 1719103098676314112