| Summary: | 碩士 === 亞東技術學院 === 資訊與通訊工程研究所 === 100 === In this study, we used the Microsoft Visual Studio(MVS) software to achieve Integrated FIR IP/Chip Design Automation(IFICDA) system, provide user a simple GUI interface to set the filter parameters, automatically synthesize the filters of optimize RTL Code, automatic synthesis of logic gates and thus the circuit simulations, and automated chip layout design in final. Validate examples of the system for several FIR digital filter chip design, and the chip performs well and the design process is smooth and simple.
CSE (Canonic Signed the Digit) algorithm [9-10] and Booth algorithms have well effectively simplification in the simplification of FIR digital filter design. However, the study found the advantages of simplification group but also concerns of overhead in simplification. That affects the effectiveness of the simplification group. We proposed a new greedy algorithm in IFICDA, first the product term of the filter coefficients are represented as the Booth and CSD as well as Mix expression using a combination of both, and then were the free-paid iterative HCSE (Horizontal Common Subexpression Elimination) simplification and effective HCSE simplification. Respectively, that solves defects of the ungrouped free-paid group and award use of over-paid grouped simplification. The definition of the SG (Select Gain) values as a criterion of group selecting in free-paid iterative HCSE simplification algorithm, this standardization of selecting of simplification group will not miss the group of better efficiency in the process of group simplification. We also defined useful measurement criteria in effective HCSE simplification, and avoid the award use of over-paid simplification. Finally, we select optimal solution from these simplifications of three represents, to generate the IP of the FIR digital filter, to export the better performance of RTL Code.
In this study, chip layout design included in IFICDA, proposed a chip design automation of CDA process based on Cell-based. CDA process generates an “ACD.scr” file automatically. In IFICDA, the ACD file uses “OitCellLibrary” of OIT Lab results of chip and application, launches Design Compiler to synthesis the logic gates using aforementioned RTL code, and then runs APR (Auto Place & Route) program by Encounter to produce the FIR digital filter chip layout design. The system is also combined with Hspice simulation, provides circuit simulation and verification of the Gate Level file.
A few various types of FIR digital filter specifications of 49taps, 20-bit word (5 integer bits + 15 float bits), have been applied in the IFICDA system for automated design verification. The efficiency of the greedy algorithm can reach more than 68.0%, and the average generation time for each chip design is also in 10 minutes. These application practical confirm the greedy algorithm improving the FIR digital filter design performance in IFICDA, from efficient RTL Code generation to quickly run through the chip design process, greatly shorten the development time of FIR digital filter chip design.
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