The technique of failure location analysis for high integrated circuit module

• Main Authors: Ming-Nung Tsai, 蔡銘濃
• Other Authors: Wen-Ray Chen
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/3u2847

碩士 === 國立虎尾科技大學 === 光電與材料科技研究所 === 99 === As electronic products go to the powerful, easy to carry, more compact size, low power, and high performance which are the trends of product design. In recent years, the semiconductor manufacturing process was highly improved and rapidly scaling down the gate lengths of CMOS, so that IC designers develop a multi-functional chip with a higher integration. However, the chip''s circuit was designed by integrating a number of features from the circuit designer. Therefore, for highly integrated circuits which all have complex interactions associated with the IC circuit, the debug processes are more difficult. The designer, in general, of the only familiar with their design of the circuit, and often ignore the problem may occur in the circuit interface module associated. Photon Emission Microscope, PEM, and IR-OBIRCH is a very useful IC failure analysis testing equipment, it provides a simple, rapid, non-destructive and high accuracy of fault location. Through the fault location precision equipment is required to analyze the outliers. It can promote the convergence of fault location; provide the circuit designers to identify design errors, and proposed amendments to plan to reduce the debugging time. This thesis is the integration of a particular type of highly integrated chip products in which the RTC (Real Time Clock) circuit module for small leakage current of the positioning. Experiments by (Photon Emission Microscope) and (IR-OBIRCH) analysis, the IC appears abnormal hot spots and highlights the position of leakage produced to identify the circuit when the IC module point of failure.