| Summary: | 碩士 === 國立臺灣科技大學 === 電機工程系 === 99 === This thesis presents two designs of radio frequency (RF) receiver front end circuits for different applications utilizing TSMC CMOS 0.18μm process. The first front end circuit operates at 900 MHz and can be applied to RFID and GSM systems. This front end operates at 1.8 V with a power consumption of 15 mW. The front end circuit consists of a low noise amplifier (LNA) and a mixer. After receiving a small high-frequency signal, the mixer amplifies and down-converts the signal amplified by the LNA into a 400 kHz medium-frequency signal. The second front end operates at 433 MHz, and is for biomedical systems. This front end operates at 1.2 V with a power consumption of 505 μW. The structure is the same as the previous one, also an LNA and a mixer. The mixer in this circuit down-converts the input signal to a medium-frequency signal of 20 kHz.
In addition, this thesis also made improvements for the first front end circuit. The improved circuit emphasizes on better linearity and better stability. Moreover, a simple voltage controlled oscillator (VCO) is added. This modification not only solves the problem of phase error caused by using external local oscillator signals (LO), but also saves the trouble of finding and connecting an external LO. The modified front end has nearly the same power consumption as the original, but has much better linearity.
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