Hardware/Software Co-design and Implementation of a Two-stage Algorithmic Processor for Hough-Transform-based Line Detection

• Main Authors: Jiang-Shiuan Huang, 黃健軒
• Other Authors: Chen-Mie Wu
• Format: Others
• Language: zh-TW
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/chw2e4

碩士 === 國立臺灣科技大學 === 電子工程系 === 99 === This thesis is related to the hardware/software co-design and verification of an algorithmic processor for an HT-based (Hough- Transform-based) two-stage line detection algorithm. The related research work includes four parts: The first part is about software design of the HT-based line detection algorithm for binary images. After analyzing the property of the HT-based algorithm and considering about the limited hardware resources in the embedded system, a two-stage HT-based algorithm for line detection has been developed. The second part is to design and implement a two-stage algorithmic processor for HT-based line detection. SDARM is used to store the whole binary images. Therefore the processor consists of source data fetching sub-processor, Hough transform sub-processor, and local max finding sub-processor. Finally, the above hardware modules are integrated into an SOPC-based system and implemented on an Altera FPGA development board. The third part is to write the related drivers for the algorithmic processor. Then the function of the algorithmic processor is verified through using a RPC-based verification system. The fourth part is about the verification and the evaluation of the run-time performance of the algorithmic processor. On the whole, the goal of this thesis is to do researches on the development of an HT-based two-stage line detection algorithm and its hardware processor. Then the related algorithmic processor is developed and implemented on the FPGA development board. After being verified by using various images, the algorithm developed in this thesis has shown very good performance. Meanwhile, it also shows that the hardware/software co-design method presented can improve the efficiency of both the design and verification flows.