Self-Calibrated Time-to-Digital Converter with 3.9ps Resolution

碩士 === 國立臺灣科技大學 === 電子工程系 === 99 === This paper provides a TDC based on pulse stretch method possesses self calibration technique. The pulse stretcher is implemented by dual-slope method. The self calibration technique uses Successive-Approximation Register (SAR) to reduce the error from process, su...

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Main Authors: SHIAU-TZA GU, 古孝澤
Other Authors: Poki Chen
Format: Others
Language:zh-TW
Published: 2011
Online Access:http://ndltd.ncl.edu.tw/handle/kw3fkm
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spelling ndltd-TW-099NTUS54280992019-05-15T20:42:06Z http://ndltd.ncl.edu.tw/handle/kw3fkm Self-Calibrated Time-to-Digital Converter with 3.9ps Resolution 具3.9微微秒解析度之自我校準式時間至數位轉換電路 SHIAU-TZA GU 古孝澤 碩士 國立臺灣科技大學 電子工程系 99 This paper provides a TDC based on pulse stretch method possesses self calibration technique. The pulse stretcher is implemented by dual-slope method. The self calibration technique uses Successive-Approximation Register (SAR) to reduce the error from process, supply voltage and ambient temperature (PVT) variation. Therefore, the precision and accuracy have low sensitivity of PVT variation. The resolution of proposed TDC reaches 3.9ps. Die area is 0.77×0.25 mm2. The power consumption is 15.4mW. The process is TSMC 1P6M 0.18μm. According to the simulation result, under process variation, supply voltage variation over 1.62V to 1.98V and ambient temperature variation over 0℃ to 100℃, the stretch factor tallies the requirement of anticipated specification. Poki Chen 陳伯奇 2011 學位論文 ; thesis 97 zh-TW
collection NDLTD
language zh-TW
format Others
sources NDLTD
description 碩士 === 國立臺灣科技大學 === 電子工程系 === 99 === This paper provides a TDC based on pulse stretch method possesses self calibration technique. The pulse stretcher is implemented by dual-slope method. The self calibration technique uses Successive-Approximation Register (SAR) to reduce the error from process, supply voltage and ambient temperature (PVT) variation. Therefore, the precision and accuracy have low sensitivity of PVT variation. The resolution of proposed TDC reaches 3.9ps. Die area is 0.77×0.25 mm2. The power consumption is 15.4mW. The process is TSMC 1P6M 0.18μm. According to the simulation result, under process variation, supply voltage variation over 1.62V to 1.98V and ambient temperature variation over 0℃ to 100℃, the stretch factor tallies the requirement of anticipated specification.
author2 Poki Chen
author_facet Poki Chen
SHIAU-TZA GU
古孝澤
author SHIAU-TZA GU
古孝澤
spellingShingle SHIAU-TZA GU
古孝澤
Self-Calibrated Time-to-Digital Converter with 3.9ps Resolution
author_sort SHIAU-TZA GU
title Self-Calibrated Time-to-Digital Converter with 3.9ps Resolution
title_short Self-Calibrated Time-to-Digital Converter with 3.9ps Resolution
title_full Self-Calibrated Time-to-Digital Converter with 3.9ps Resolution
title_fullStr Self-Calibrated Time-to-Digital Converter with 3.9ps Resolution
title_full_unstemmed Self-Calibrated Time-to-Digital Converter with 3.9ps Resolution
title_sort self-calibrated time-to-digital converter with 3.9ps resolution
publishDate 2011
url http://ndltd.ncl.edu.tw/handle/kw3fkm
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