DESIGN OF A LOW POWER HIGH PERFORMANCE TWO'S COMPLEMENT GENERATOR WITH SMALL AREA
碩士 === 國立臺灣科技大學 === 電子工程系 === 99 === In this thesis, a low-power high-performance two's complement generator chip design based on fast-finding one approach (FFO) operation is proposed. It achieves high- speed with fewer CMOS transistors to reduce area, and to achieve rapid conversion of the two...
Main Authors: | San-ting Chang, 張善婷 |
---|---|
Other Authors: | Shanq-Jang Ruan |
Format: | Others |
Language: | en_US |
Published: |
2011
|
Online Access: | http://ndltd.ncl.edu.tw/handle/r8wn9t |
Similar Items
-
Complemented Response Cell (CRC) : A Low Peak Power design for Testability Technique
by: Bo-Hua Chen, et al.
Published: (2006) -
High-Performance and Low-Power 1024-bit RSA Hardware Design
by: Nai-Jen Chang, et al.
Published: (2005) -
High-Performance and Low-Power 1024-bit RSA Hardware Design
by: Nai-Jen Chang, et al.
Published: (2005) -
Design of The Crushing Type Power Generation Device
by: Shsn-Jie Yang, et al.
Published: (2014) -
Low-Power and Area-Efficient Viterbi Decoder Design and Its IP Generator
by: Der-Wei Yang, et al.
Published: (2008)