DESIGN OF A LOW POWER HIGH PERFORMANCE TWO'S COMPLEMENT GENERATOR WITH SMALL AREA

• Main Authors: San-ting Chang, 張善婷
• Other Authors: Shanq-Jang Ruan
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/r8wn9t

碩士 === 國立臺灣科技大學 === 電子工程系 === 99 === In this thesis, a low-power high-performance two's complement generator chip design based on fast-finding one approach (FFO) operation is proposed. It achieves high- speed with fewer CMOS transistors to reduce area, and to achieve rapid conversion of the two's complement arithmetic. Many digital filters are widely implemented in hardware using two's complement arithmetic. In order to effectively reduce the area, this thesis proposes a CMOS transistor architecture with the FFO operation which utilizes a multiplexer architecture to select the correct two's complement value. The proposed architecture further improves the following two drawbacks. One is that the conventional two's complement circuit is designed by inversion-add-one scheme which results in high power consumption by using high amount of logic gates. The other is that in the OR-XOR circuit, the FFO approach has lowed power consumption, and the length of the input bit increases proportionally with the hardware area; therefore, the proposed implementation with the FFO approach not only reduces the area of the circuit but also improves the power consumption. In addition, the proposed method avoids the non-negligible propagation delay. Circuit validation of the chip shows that the proposed scheme achieves not only at least 67% power improvement but also 68% circuit area reduction with significant performance improvement comparing to the conventional one.