The Design and Verification of High-Speed Redundant Booth Multiplier

• Main Authors: Min-Lun Yuan, 袁民倫
• Other Authors: Ming-Bo Lin
• Format: Others
• Language: zh-TW
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/t2bdn5

碩士 === 國立臺灣科技大學 === 電子工程系 === 99 === In this thesis, a Booth multiplier with redundant number system is proposed. The radix-4 redundant Booth multiplier and radix-16 redundant Booth multiplier are combined with the positive-negative complement redundant encoding. In order to improve the performance of the redundant Booth multiplier, we redesign the redundant Booth encoding unit and compression tree unit. In addition, we apply a high-speed signed redundant binary presentation to two’s complement binary presentation converter to meliorate the performance of redundant Booth Multiplier. Besides, six redundant multipliers of different data widths based on radix-4 and radix-16 Booth algorithms are implemented. The data width includes 8 bits, 16 bits, 24 bits, 32 bits, 48 bits and up to 64 bits. The effects of performance, power and hardware cost of differ radixes and data widths are discussed. A 16-bit radix-4 redundant Booth and radix-16 redundant Booth multipliers are implemented and verified with Xilinx Virtex-5 ML505- V5LX110T FPGA and TSMC 0.18 μm cell library. When implemented on FPGA, the 16-bit radix-4 redundant Booth and radix-16 Booth multipliers consume 786 and 761 LUTs, respectively, and their working frequencies can reach 100 MHz. When implemented with the cell library, two multipliers have the same core area of about 600×630 μm2 and the whole chip occupies 970×1000 μm2. The average power consumption with 100 MHz data input rate is 1.75 mW for radix-4 redundant Booth multiplier and 1.58 mW for radix-16 Booth multiplier, respectively.