| Summary: | 博士 === 國立臺灣大學 === 電機工程學研究所 === 99 === ABSTRACT
Since the explosive growth of wireless communication systems and portable consumer electronics, the low-power low-voltage integrated circuits are indispensable. Many of the applications utilize the digital signal processing to resolve the transmitted information. Therefore, an analog-to-digital converter (ADC) is required between the analog signal and the DSP system. The trend of increasing integration level for integrated circuits has forced the ADC to reside on the same silicon with large DSP and digital circuits. These ADCs operate with the digital circuits in the same voltage which is desirable. Digital circuit design benefits with higher speed, small power, small area, cost-down from state-of-the-art CMOS technologies. For ADC design, the voltage supply and the intrinsic device gain are decreased that are difficult to achieve a high-gain wide-bandwidth amplifier. Besides, the dynamic range of signal is reduced that decreases effective number of bits (ENOB) in ADC circuit. Therefore, The ADC design is becoming a bottleneck in the advance CMOS process.
In this paper presents three proposed techniques to resolve these limitations in ADC. First, a pipelined ADC with folded S/H is presented. This method achieves a half swing operation in op-amp based MDAC, and saves about half of pipelined ADC circuits. Second, an op-amp-free MDAC is presented. We propose a zero-crossing based circuit to develop a simple, fast, low power, small area pipelined ADC. This research suits to address scaling issues. These techniques are proposed for ADC designer who can implement an efficient pipelined ADC in advance technology. Finally, we develop time-domain type ADC that more suit for digital CMOS process.
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