| Summary: | 碩士 === 國立臺灣大學 === 電機工程學研究所 === 99 === In high speed communication, the speed of serial communication has been increased to gigabits per second. The modern trend of high speed communication system converted the transmission medium from copper wire to fibre gradually. In the receiver side of networks, Clock and data recovery circuit (CDR) plays an important role for local area network (LANs) and wide area networks (WANS). The CDR circuit generates a clock that synchronizes with received data and removes the received data jitter. CMOS technologies are often employed in high-speed circuits now because of the low cost, low power dissipation and highly integrated capability.
CDR circuit usually uses inductors to expend the operation rate. However, the chip size must increase seriously because inductors occupy large area in die. It doesn’t benefit the modern trend, system on chip (SOC). On the other hand, the CDR should able to work in different speeds for different specifications. So an inductorless half-rate clock and data recovery circuit (6Gb/s-7.7Gb/s) was proposed. It is composed of a linear half-rate PD which can suppress jitter in retimed data and relax the design difficulty of VCO, a dual tuning VCO which have two independent tuning control voltage in order to reduce the clock jitter, finally, a reference-less FD which includes frequency locked detector that makes the FD is no output after frequency acquisition. The CDR was fabricated in TSMC 90nm 1P9M CMOS technology with an area of 0.58x0.58mm^2. The output clock jitter of this proposed CDR is measured 78ps (peak-to-peak) and 12.64ps (rms) for 6Gb/s 27-1 PRBS. The power dissipation of the core circuit is 75.2mW under 1.2V power supply.
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