Electrical Modeling and Design for Signal Integrity of Area-Array Vertical Interconnects in Electronic Packaging

• Main Authors: Ruey-Bo Sun, 孫瑞伯
• Other Authors: 吳瑞北
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/60943366541212561875

博士 === 國立臺灣大學 === 電信工程學研究所 === 99 === In order to optimize the electrical performance of electronic packaging, the electrical modeling and designs for signal integrity (SI) of vertical interconnects are the considerably critical issues. In this dissertation, the various significant kinds of noises, including reflection, crosstalk, simultaneous switching noise (SSN), and substrate loss in the area-array vertical interconnects, are investigated by taking three different types of vertical interconnects, consisting of pin type (pogo pin), ball-shape type (bump and solder ball), and via type (through silicon via, TSV) as examples. A series of novel and systematic methodologies are proposed for the investigations and noise suppression. With regard to the analysis and suppression of SSN, this dissertation takes a bump grid array as an example to propose a systematic design methodology, acquiring the optimal signal-ground assignment with the minimized loop SSN by using genetic algorithm (GA). For the reduction of computing complexity, a new circuit simplification method is developed to simplify a complete I/O buffer circuits, including package traces and a bump array, into a circuit of inductors and current sources together with its applicable range derived analytically. Based on the optimized results, the optimal signal-to-ground ratio and its associated bump assignments are obtained. Also, some heuristic designs are proposed, accordingly. As for suppressions of the reflection and crosstalk, designs of the impedance match and crosstalk reduction for all possible signal-ground assignments are very challenging. In this dissertation, a novel compromise impedance match design is proposed for a pogo pin array with the diverse pin assignments to find the permissible window of the pogo pin geometries and the upper bound of operating frequency such that all pin patterns meet the specification on return loss. Two different types of design charts are developed to greatly facilitate the design. The first one is the equivalent impedance of pogo pin versus the pin radius-to-pitch ratio. The second one is a much general chart in terms of the reflection coefficient versus the electrical length and the relative impedance difference of the pogo pin. On the other hand, for the sake of the crosstalk reduction in the pogo pin array, a new isolation structure directly integrated in a test socket is proposed. The isolation structure is appropriately designed by adopting the full-wave and quasi-static methods so that the reflection and crosstalk for all pin patterns are both smaller than -20 dB over dc to 10 GHz. The measured S parameters obtained by using the new test fixtures have good correlations with simulated ones, validating the proposed ideas and methodologies. Regarding to the suppression of dispersion noise due to the substrate loss, the equalization technique can be introduced to compensate the lossy effect. Considering the TSV interconnect in the three-dimensional integrated circuit (3D IC), a novel passive equalizer capable of the perfect compensation for lossy effects of TSV is devised. It is only composed of a parallel resistance-capacitance (RC) circuit. To design the equalizer, the analytic circuit model of TSV is derived and substantiated up to 20 GHz, and based on which, the novel significance analysis is implemented to inspect the relative importance of each parasitic element, thereby attaining a much simplified capacitance-conductance (CG) circuit model. It proves that the first order effects of TSV are attributed to the oxide liner and the lossy silicon substrate. The design theory and formulas of the equalizer can also be derived accordingly. The output eye diagram of multi-stacked TSVs in series with the designed equalizer is nearly open with zero timing jitter.