Design of Through Silicon Via Assignments for Minimizing Simultaneous Switching Noise in 3D IC
碩士 === 國立臺灣大學 === 電信工程學研究所 === 99 === Toward the design trends of high clock frequencies, high power density, low voltage levels, and small size for high-speed digital systems, the simultaneous switching noise (SSN) or ground bounce noise (GBN) in the circuits is becoming one of the major challeng...
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| Format: | Others |
| Language: | zh-TW |
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2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/34848833533724567649 |