Design of a Dynamic Self-Reconfigurable on-Chip Interconnection Network

• Main Authors: Ying-Cherng Lan, 籃英誠
• Other Authors: 陳少傑
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/49254373420406673585

博士 === 國立臺灣大學 === 電子工程學研究所 === 99 === A Bidirectional channel Network-on-Chip (BiNoC) architecture is proposed in this Dissertation to enhance the performance of on-chip communication while keeping the implementation cost efficient. In a BiNoC, each communication channel allows to be dynamically self-reconfigured to transmit flits in either direction. This added flexibility can be easily fitted into most of the state-of-the-art conventional NoC designs and promises better bandwidth utilization, lower packet delivery latency, and higher packet consumption rate. The novel on-chip BiNoC router architecture is developed to support dynamic self-reconfiguration in the bidirectional traffic flow. The flow direction at each channel is decided by a channel-direction control protocol that is high-performance, free of deadlock, and free of starvation. In addition, a QoS-aware bidirectional arbitration scheme is integrated to ensure various service requirements such as best-effort, guaranteed-service, and guaranteed-throughput. Furthermore, with our proposed novel virtual-channel management, BiNoC can reduce head-of-line blocking without increasing the number of virtual-channels (VCs) thus improves performance while keeping low implementation cost. Experimental results using both synthetic traffic patterns and E3S benchmarks verified that the proposed BiNoC architecture can significantly reduce the traffic delivery latency at all levels of traffic injection rates. Besides, the proposed QoS control mechanism can significantly improve the channel utilization for latency-sensitive traffics while keeping sufficient bandwidth for throughput-sensitive ones. Finally, it is very encouraging that the BiNoC can improve traffic delivering efficiency and achieve the goal of power and area saving by increasing bandwidth utilization flexibility and reducing the physical volume of buffer requirements.