Chip Realization of 0.8V Bulk CMOS DTMOS Technique for Optimization of Low-Power System Applications
碩士 === 國立臺灣大學 === 電子工程學研究所 === 99 === The thesis describes the CHIP realization of 0.8v bulk CMOS DTMOS technique for optimization of low power system application. First, introduction on the low power, low voltage trends on CMOS SOC is described in chapter 1. Then a bulk PMOS DTMOS technique usi...
| Main Authors: | , |
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| Format: | Others |
| Language: | zh-TW |
| Published: |
2011
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| Online Access: | http://ndltd.ncl.edu.tw/handle/45116602938858725816 |