Chip Realization of 0.8V Bulk CMOS DTMOS Technique for Optimization of Low-Power System Applications

碩士 === 國立臺灣大學 === 電子工程學研究所 === 99 === The thesis describes the CHIP realization of 0.8v bulk CMOS DTMOS technique for optimization of low power system application. First, introduction on the low power, low voltage trends on CMOS SOC is described in chapter 1. Then a bulk PMOS DTMOS technique usi...

Full description

Bibliographic Details
Main Authors:	Cheng-Jiun Dai, 戴承雋
Other Authors:	郭正邦
Format:	Others
Language:	zh-TW
Published:	2011
Online Access:	http://ndltd.ncl.edu.tw/handle/45116602938858725816

id	ndltd-TW-099NTU05428118
record_format	oai_dc
spelling	ndltd-TW-099NTU054281182015-10-16T04:03:09Z http://ndltd.ncl.edu.tw/handle/45116602938858725816 Chip Realization of 0.8V Bulk CMOS DTMOS Technique for Optimization of Low-Power System Applications 實現0.8V基體互補式金氧半動態臨限電壓技術設計低功率系統晶片應用 Cheng-Jiun Dai 戴承雋碩士國立臺灣大學電子工程學研究所 99 The thesis describes the CHIP realization of 0.8v bulk CMOS DTMOS technique for optimization of low power system application. First, introduction on the low power, low voltage trends on CMOS SOC is described in chapter 1. Then a bulk PMOS DTMOS technique using MTCMOS and DTMOS technology is presented in chapter 2. Then the approach of chip realization in terms of integration of EDA tools for implementation an SOC chip using the bulk PMOS DTMOS technique is described. In chapter 3, detailed analysis of a test chip a 0.8v 16bit multiplier using the bulk PMOS DTMOS technique via the developed chip implementation technique using integrated EDA tools is described. 郭正邦 2011 學位論文 ; thesis 46 zh-TW
collection	NDLTD
language	zh-TW
format	Others
sources	NDLTD
description	碩士 === 國立臺灣大學 === 電子工程學研究所 === 99 === The thesis describes the CHIP realization of 0.8v bulk CMOS DTMOS technique for optimization of low power system application. First, introduction on the low power, low voltage trends on CMOS SOC is described in chapter 1. Then a bulk PMOS DTMOS technique using MTCMOS and DTMOS technology is presented in chapter 2. Then the approach of chip realization in terms of integration of EDA tools for implementation an SOC chip using the bulk PMOS DTMOS technique is described. In chapter 3, detailed analysis of a test chip a 0.8v 16bit multiplier using the bulk PMOS DTMOS technique via the developed chip implementation technique using integrated EDA tools is described.
author2	郭正邦
author_facet	郭正邦 Cheng-Jiun Dai 戴承雋
author	Cheng-Jiun Dai 戴承雋
spellingShingle	Cheng-Jiun Dai 戴承雋 Chip Realization of 0.8V Bulk CMOS DTMOS Technique for Optimization of Low-Power System Applications
author_sort	Cheng-Jiun Dai
title	Chip Realization of 0.8V Bulk CMOS DTMOS Technique for Optimization of Low-Power System Applications
title_short	Chip Realization of 0.8V Bulk CMOS DTMOS Technique for Optimization of Low-Power System Applications
title_full	Chip Realization of 0.8V Bulk CMOS DTMOS Technique for Optimization of Low-Power System Applications
title_fullStr	Chip Realization of 0.8V Bulk CMOS DTMOS Technique for Optimization of Low-Power System Applications
title_full_unstemmed	Chip Realization of 0.8V Bulk CMOS DTMOS Technique for Optimization of Low-Power System Applications
title_sort	chip realization of 0.8v bulk cmos dtmos technique for optimization of low-power system applications
publishDate	2011
url	http://ndltd.ncl.edu.tw/handle/45116602938858725816
work_keys_str_mv	AT chengjiundai chiprealizationof08vbulkcmosdtmostechniqueforoptimizationoflowpowersystemapplications AT dàichéngjuàn chiprealizationof08vbulkcmosdtmostechniqueforoptimizationoflowpowersystemapplications AT chengjiundai shíxiàn08vjītǐhùbǔshìjīnyǎngbàndòngtàilínxiàndiànyājìshùshèjìdīgōnglǜxìtǒngjīngpiànyīngyòng AT dàichéngjuàn shíxiàn08vjītǐhùbǔshìjīnyǎngbàndòngtàilínxiàndiànyājìshùshèjìdīgōnglǜxìtǒngjīngpiànyīngyòng
_version_	1718092068100767744

Chip Realization of 0.8V Bulk CMOS DTMOS Technique for Optimization of Low-Power System Applications

Similar Items