Integer-N and Fractional-N Low Power Frequency Synthesizers for Zigbee System

• Main Authors: Shuo-Wen Chang, 張碩文
• Other Authors: 呂學士
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/41962602791753033398

碩士 === 國立臺灣大學 === 電子工程學研究所 === 99 === An integer-N and a fractional-N frequency synthesizers for Zigbee standard are realized in TSMC 0.18-um process are presented in this thesis, and the frequency bands of the operation are also cover 2.4GHz~2.48GHz (Zigbee band). Zigbee is a wireless protocol which is similar to Bluetooth, and it has some features, such as low power, low data rate, and low cost. Two frequency synthesizers are introduced as follows: The first chip is an integer-N frequency synthesizer for Zigbee standard. The whole system is operated at a low supply voltage 1.2-V in order to lower the power consumption. In addition, forward body-biasing technique and reverse short channel effect are used to lower the requirement of the supply voltage in the frequency synthesizers. According to the measurement results we can know the whole frequency synthesizer only consumes 12.62 mW. The second chip is a fractional-N frequency synthesizer for Zigbee standard. This frequency synthesizer is operated at a low supply voltage 1.2-V, which is the same as the first one chip. A delta-sigma modulator is adopted in this circuit to implement the fractional-N frequency synthesizer due to its lower spurs magnitude and high-pass noise shaping ability. In addition, a technique of the two-point channel control is used to add an additional high-pass control path to tune the VCO in order to reduce the PLL settling time. Furthermore, the power consumption of the wireless transceiver can be reduced. According to the measurement results we can know the PLL settling time is reduced to 36us. Finally, we compare advantages and shortcomings in these two frequency synthesizers according to the measurement results, and make a conclusion