Process Development and Characterization of MOS Capacitor with Ultra-thin Oxide

• Main Authors: Tzu-Yu Chen, 陳姿妤
• Other Authors: Jenn-Gwo Hwu
• Format: Others
• Language: en_US
• Published: 2011
• Online Access: http://ndltd.ncl.edu.tw/handle/28318437433064888086

碩士 === 國立臺灣大學 === 電子工程學研究所 === 99 === Process development and the characterization of MOS capacitor with ultra-thin oxide were explored in this thesis for the ultra-thin gate oxide becomes the mainstream nowadays. The influence of residual ions and gases at the Si/SiO2 interface in metal-oxide-semiconductor (MOS) structure was investigated in chapter 2. A new processing step, room temperature (RT) vacuum treatment, was proposed to study the influence of them on the characteristics of the interface. Treatment sample was placed under low nitrogen pressure at room temperature after oxidation but before post-oxidation annealing (POA). The oxide thicknesses, flat-band voltage (VFB) shifts, interface trap densities (Dit), capacitance-voltage (C-V) characteristics, and leakage current were discussed between the treatment and control samples. There were two parts in chapter 3. In the first part, a new methodology to extract ultra-thin gate oxide thickness was proposed. Oxide flat-band voltage (VOX, FB) was well defined in this study as compared with the conventional VFB. Based on the current density at VOX, FB obtained from the experimental data and the plotted natural logarithm of current density at VOX, FB versus oxide thickness, ultra-thin oxide layer thickness can be extracted easily. In the second part, MOS capacitor memory phenomenon was studied. After applying -2.5 V and +2.5 V for a while, there are two current states in the I-V curves and two capacitance states in the C-V curves of weak inversion region by the repelling and recovery of OH- at the edge of gate electrode in oxide layer. Due to existing of two states current and capacitance, there is a capability for this device to be applied to memory device in the future.