An IEEE 1500 Compatible Test Wrapper for SoC Debug
碩士 === 國立臺灣大學 === 電子工程學研究所 === 99 === This thesis presents an IEEE 1500 compatible debug test wrapper (DTW) technique to identify the first failing core, the failing cycle and the failing core output in SoC. A two-level design-for-debug (DfD) is proposed in DTW. The firstlevel DfD identifies the fai...
| Main Authors: | , |
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| Other Authors: | |
| Format: | Others |
| Language: | en_US |
| Published: |
2010
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| Online Access: | http://ndltd.ncl.edu.tw/handle/26551354317408551543 |