| Summary: | 碩士 === 國立臺灣大學 === 電子工程學研究所 === 99 === This thesis presents an IEEE 1500 compatible debug test wrapper (DTW)
technique to identify the first failing core, the failing cycle and the failing core
output in SoC. A two-level design-for-debug (DfD) is proposed in DTW. The firstlevel
DfD identifies the failing core by observing the multiple-input serial register
(MISR) signature. In addition, the failing cycle is limited within a period of cycles,
which is called the suspect window. The second-level DfD identifies the failing cycle
and the failing core output by observing the BCH outputs every cycle in the suspect
window. The experiments on ISCAS ’89 circuits show that, on average, the BCH
detection latency is 0. The detection latency measures the time between error
occurence and detection by proposed DfD. The emulation of the digital photo frame
SoC shows that DTW can identify the first failing core and the failing cycle. The
synthesis results of DTW show that DTW supports at-speed debugging with small
area overhead (approximately 2%) for ARM926.
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