Joint I/Q Imbalance Compensation and Channel Equalization forSTBC MISO/MIMO OFDM Systems, and FPGA Design

• Main Authors: Yi-Hung Lin, 林宜宏
• Other Authors: Chorng-Kuang Wang
• Format: Others
• Language: en_US
• Published: 2010
• Online Access: http://ndltd.ncl.edu.tw/handle/27670229255899435091

碩士 === 國立臺灣大學 === 電子工程學研究所 === 99 === In this thesis, the joint I/Q imbalance compensation and channel equalization and the start up self-calibration algorithm of I/Q imbalance are proposed. The IEEE 802.11n MISO/MIMO OFDM transceiver is adopted as a test vehicle to demonstrate the presented algorithm. The self-calibration algorithm is performed at transceiver start-up to estimate the end user I/Q imbalance parameter, including phase and gain mismatch. Therefore, the Tx/Rx I/Q imbalance of end user can be alleviated by self calibration and compensation. In addition, the start-up self calibration and compensation can make conventional CFO estimation and compensation more reliable under end user Rx I/Q imbalance impairment. Although Rx I/Q imbalance self compensation and CFO have been compensated, the remote Tx I/Q imbalance and quasi-static channel variation degrade the system performance. Therefore, based on MMSE criteria, the joint I/Q imbalance compensation and channel equalization is presented to minimize the remote Tx I/Q imbalance and quasi-static channel variation during the physical data transmission. Consequently, the performance improvement is 2-dB compared with LS algorithm. On the other hand, the cost-e cient architecture of joint I/Q imbalance compensation and channel equalization is proposed to reduce hardware complexity based on strength-reduced transformation. The cost e cient architecture of joint I/Q imbalance and channel equalization contains three parts: MIMO detection, updating process and channel estimation. The overall architecture obtains the 35% reduction e ciency in multiplication. Furthermore, The uncoded SER of this design is the same as the direct implementation. Finally, the joint I/Q imbalance compensation and channel equalization is realized by FPGA board EP1S80 at 40MHz and the system evaluations are measured by Tektronix TLA715 pattern generator and logic analyzer.